1. Field of the Invention
The present invention relates to a clock control apparatus and method for a memory controller for reduction of power consumption. More specifically, the present invention relates to a clock control apparatus and method that controls the clock signal to an internal circuit of a memory controller and the clock enable signal CKE to SDRAM when accessing image data of SDRAM per block or per line.
The clock control apparatus and method of the present invention are applicable to a memory controller of SDRAM for real-time processing applications, such as MPEG CODEC LSI or digital-broadcasting receivers, in order to effectively carry out reduction of power consumption of the memory controller when there is a definite access factor.
2. Description of the Related Art
SDRAM has various characteristics, such as the input/output circuit composition synchronized with the external clock, the command-format access capability, the continuous access capability by burst transmission, and the plural-bank composition.
Generally, when accessing image data of SDRAM, the clock enable signal CKE is set at “H” level. By supplying the bank active command (BANK ACTIVE) first, the row address of a memory location being accessed is given to the SDRAM. By supplying the read/write command (READ/WRITE) secondly, the column address of the memory location is given to the SDRAM.
The receiving of such commands by the SDRAM is performed in synchronism with the clock signal input to SDRAM.
The SDRAM is set in the active state in response to the received bank active command (BANK ACTIVE). The active state of the SDRAM is maintained until the precharge command (PRECHARGE) is subsequently input to the SDRAM.
In Japanese Laid-Open Patent Application No. 9-180438, a conventional memory controller including the function of controlling the clock enable signal (CKE) is given. The conventional memory controller is provided to perform the access control of a general-purpose SDRAM. The clock control function of the conventional memory controller is used to reduce the power consumption of SDRAM.
In the above-mentioned memory controller, when the access request is sent to SDRAM, the state of the clock enable signal CKE is changed from the inactive state to the active state. When the accessing of the general-purpose SDRAM is finished, the state of the clock enable signal CKE is returned from the active state to the inactive state. Thereby, the power consumption of the general-purpose SDRAM is reduced.
Unlike the above-mentioned memory controller of the general-purpose SDRAM, in a case of a memory controller of SDRAM for real-time processing applications, such as MPEG CODEC LSI or digital-broadcasting receivers, there is a definite access factor, and the efficiency of real-time processing must be increased.
In the case of the memory controller of the SDRAM for real-time processing applications, a sequence of several macro commands is collectively issued when accessing the SDRAM, which is different from the case of the memory controller of the general-purpose SDRAM. Hence, when the memory controller of SDRAM for real-time processing applications performs the clock control of the SDRAM for reduction of power consumption, it is necessary to perform the clock control for the entire sequence of such macro commands, not for a signal access to the data in the general-purpose SDRAM.
FIG. 1A and FIG. 1B are diagrams for explaining a clock control method of a conventional memory controller, which performs access control of a general-purpose SDRAM for reduction of power consumption.
For the sake of convenience of description, the conventional memory controller as shown in FIG. 1A and FIG. 1B will be called the general-purpose SDRAM controller.
FIG. 1A shows the function of a state control circuit of the general-purpose SDRAM controller to manage the active and inactive states of the general-purpose SDRAM. FIG. 1B is a time chart for explaining a change of the states of the general-purpose SDRAM when a back active command, a read/write command and a precharge command are input to the general-purpose SDRAM controller.
As shown in FIG. 1B, when the access request (REQUEST) occurs to the general-purpose SDRAM, the first read/write access is given to the general-purpose SDRAM with the clock enable signal (CKE) that is still in the inactive state. At this time, the state of the CKE in the general-purpose SDRAM is changed to the active state.
As shown in FIG. 1B, the general-purpose SDRAM changes to the active state, when the access request (REQUEST) occurs.
According to this access request, the clock enable signal CKE will rise and will be in the active state.
When the bank active command (BANK ACTIVE) following the access request is inputted, the clock enable signal CKE is the active state.
As shown in FIG. 1A, the state control circuit of the general-purpose SDRAM controller sets the clock enable signal CKE as the active state from the inactive state, when SDRAM shifts to the active state from the inactive state.
As shown in FIG. 1A, the state control circuit of the general-purpose SDRAM controller sets the clock enable signal CKE as the inactive state from the active state, when SDRAM shifts to the inactive state from the active state.
In the clock control by the general-purpose SDRAM controller as shown in FIG. 1B, there is the problem that it can respond only when the access unit is the single bank.
Moreover, in the case of the conventional general-purpose SDRAM controller, it is not taken into consideration about power saving of the internal circuit of the memory controller itself.
In SDRAM for real-time-processing applications, which, on the other hand, processes the image data of the MPEG specification, the frequency of small block access is high.
That is, by the memory controller of SDRAM for real-time-processing applications, the control in the case of accessing the image data on SDRAM per the block unit or line will be the requisite.
FIG. 2A and FIG. 2B are diagrams for explaining an example of a macro access to a plurality of banks of SDRAM.
In the following explanation, it is called macro access to process a series of commands in the block unit or the line unit to two or more banks of SDRAM.
FIG. 2A shows the access unit in case a macro access to data with the block size 4×4 is performed. FIG. 2B shows the command sequence, which creates interleaved access to each bank in the macro access of FIG. 2A.
As shown in FIG. 2B, by the memory controller of SDRAM for real-time-processing applications, the approach of macro access of creating interleaved access is adopted.
When the method of macro access shown in FIG. 2B is used, the access effectiveness of SDRAM for real-time-processing applications can be improved.